Conventionally, clock data recovery (CDR: Clock Data Recovery) technology is known. With this CDR technology, in a system where a unidirectional high-speed serial signal line and a low-speed control signal line are provided between the transmission device and the receiving device, a serial data signal embedded with a clock is sent from the transmission device via the high-speed serial signal line, and the receiving device restores the data and clock based on the serial data signal. Subsequently, the system reproduces the recovered clock (recovery clock), compares the phase of the edge of the data and clock to adjust the phase, and thereby acquires accurate data.
Meanwhile, if the bit rate of the serial data signal that is sent from the transmission device is changed, an abnormal clock is reproduced in the receiving device, and erroneous data may be acquired. In order to overcome the foregoing problem, the receiving device implements processing for confirming the changed bit rate that is sent from the transmission device, and the transmission device sends a serial data signal including the changed bit rate to the receiving device after the foregoing processing.
In order to implement the foregoing processing, it is necessary to transfer a command such as a bit rate change notice or the like between the transmission device and the receiving device. Thus, for instance, the display port described in Non-Patent Document 1 is provided with a high-speed serial signal line, and a low-speed control signal line capable of interactive communication. The display port described in Cited Document 1 is able to transfer a command for confirming the bit rate with the interactive communication control signal line.